The present invention relates to circuitry for power-over-network devices, such as power-over-Ethernet (“POE”) devices, that are powered by a network data cable rather than a separate power source. More particularly, the present invention relates to integrated, on-chip relay circuitry for such network devices.
One recent advance with respect to Ethernet network technology has been in the development of power-over-Ethernet devices. As the name suggests, POE devices are powered solely by the Ethernet cable to which they are connected and therefore do not require power from an external AC power source. U.S. patent application Ser. No. 10/098,865, filed on Mar. 15, 2002, for example, describes systems and methods for detecting network devices such as POE devices that are connected to a network and for subsequently supplying power to those connected network devices via a separately connected power-supplying network device. Particularly, application Ser. No. 10/098,865 describes a technique for detecting the presence of a power-over-network device that is capable of being powered on through a network connection, in which the power-supplying device generates a series of test signals and checks whether an appropriate response is received. In order to provide the appropriate response to the power-supplying device, the power-over-network device may include filter circuitry for processing the test signals so that they may ultimately be recognized by the power-supplying device, in addition to relay circuitry that is in a closed-switch state during the detection period in order to relay the filtered test signals to the power-supplying device. Once the power-supplying network device detects a response from the power-on capable device, it then begins to supply power across the network link. Also at that time, the relay circuitry of the power-over-network device switches open and a separate switching circuitry switches closed so that the normal operation of the power-over-network device may commence.
Traditionally, the relay circuitry described above for such power-over-network devices are implemented off-chip and external from the rest of the device circuitry. One notable disadvantage caused by implementing the relay circuitry off-chip is the added cost of the circuitry due to a relative increase in the amount of required die. Therefore, in view of the foregoing, it would be desirable to design relay circuitry that is implemented on-chip with the other circuitry of a power-over-network device. It would further be desirable to design on-chip relay circuitry that is configured to relay the test signals transmitted by power-supplying devices without power and with minimal signal degradation so as to reduce the probability of failure during device detection and to thereby make the system more robust. It would be desirable to design on-chip relay circuitry that is integrated with the previously described switching circuitry in order to further increase the performance of and reduce the size and cost of the power-over-network device.